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CML Semiconductor Products
Analogue Control Interface
1.0 Features * Multiplexed 4 Input ADC 10-Bit Resolution
FX839
D/839/4 September 1997 Advance Information
* Three DACs 8 or 10-Bit Resolution
* Custom IRQ Generator with Variable * Scalable ADC Clock Frequencies 8-Bit Reference Settings from Xtal/Clock * Two Variable Attenuators * Low Power (3.0V Operation) * Serial Interface to Host C * 24-Pin SSOP Package
1.1
Brief Description
This product comprises a selection of independent functional blocks vital to modern microcomputer controlled radio-frequency communications equipment. Examples of possible uses are as follows: * * * The four-way multiplexed ADC with magnitude comparator may be used for monitoring RSSI, battery voltage, temperatures, reflected signals or error voltages. The three DACs may be used to adjust VCOs, reference oscillators, power output, bias current or IF gain. The two variable attenuators may be used to adjust deviation, modulation depth or baseband gain.
The FX839 is controlled via the standard serial 'C-BUS'. This is complementary to, and compatible with, many standard microcomputers and other baseband processing blocks.
(c) 1997 Consumer Microcircuits Limited
Analogue Control Interface
FX839
CONTENTS Section Page
1.0 Features .......................................................................................................... 1 1.1 Brief Description ............................................................................................ 1 1.2 Block Diagram ................................................................................................ 3 1.3 Signal List ....................................................................................................... 4 1.4 External Components .................................................................................... 6 1.5 General Description ....................................................................................... 7 1.5.1 Software Description ..................................................................... 8 1.6 Application Notes......................................................................................... 15 1.6.1 General.......................................................................................... 15 1.7 Performance Specification.......................................................................... 16 1.7.1 Electrical Performance ................................................................ 16 1.7.2 Packaging ..................................................................................... 21
Note:
As this product is still in development, it is likely that a number of changes and additions will be made to this specification. Items marked TBD or left blank will be included in later issues. Information in this data sheet should not be relied upon for final product design.
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1.2
Block Diagram
Figure 1: Block Diagram
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1.3
Signal List
Signal Description
Package P4/D2/D5 Pin No. 1 2 Name XTALN
Type O/P I/P The inverter output of the on-chip oscillator. The input to the on-chip oscillator, for external Xtal circuit or clock. The 'C-BUS' serial clock input. This clock, produced by the Controller, is used for transfer timing of commands and data to and from the device. See 'C-BUS' Timing Diagram (Figure 4). The 'C-BUS' serial data input from the Controller. Data is loaded into this device in 8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronised to the SERIAL CLOCK. See 'C-BUS' Timing Diagram (Figure 4). The 'C-BUS' serial data output to the Controller. The transmission of REPLY DATA bytes is synchronised to the SERIAL CLOCK under the control of the CSN input. This 3-state output is held at high impedance when not sending data to the Controller. See 'C-BUS' Timing Diagram (Figure 4). The 'C-BUS' data loading control function: this input is provided by the Controller. Data transfer sequences are initiated, completed or aborted by the CSN signal. See 'C-BUS' Timing Diagram (Figure 4). This output indicates an interrupt condition to the Controller by going to a logic '0'. This is a 'wire-ORable' output, enabling the connection of up to 8 peripherals to 1 interrupt port on the Controller. This pin has a low impedance pulldown to logic '0' when active and a highimpedance when inactive. An external pullup resistor is required. The conditions that cause interrupts are indicated in the IRQ FLAG register and are effective if not disabled.
XTAL/CLOCK
3
SERIAL CLOCK
I/P
4
COMMAND DATA
I/P
5
REPLY DATA
O/P
6
CSN
I/P
7
IRQN
O/P
8 9
ADCIN1 ADCIN2
I/P I/P
Analogue to digital converter input 1 (ADC1) Analogue to digital converter input 2 (ADC2)
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1.3
Signal List (continued)
Signal Description
Package P4/D2/D5 Pin No. 10 11 12 Name ADCIN3 ADCIN4 VSS
Type I/P I/P POWER Analogue to digital converter input 3 (ADC3) Analogue to digital converter input 4 (ADC4) The negative supply rail (ground) for both analogue and digital supplies. An analogue bias line for the internal circuitry, held at 1/2 AVDD. This pin must be decoupled by a capacitor mounted close to the device pins. No internal connection. Do not make any connection to this pin. Digital to analogue converter No. 1 output (DAC1) Digital to analogue converter No. 2 output (DAC2) Digital to analogue converter No. 3 output (DAC3) No internal connection. Do not make any connection to this pin. The positive analogue supply rail. Analogue levels and voltages are dependent upon this supply. This pin should be decoupled to VSS by a capacitor. Input to MOD1 variable attenuator. Input to MOD2 variable attenuator. Output of MOD1 variable attenuator. Output of MOD2 variable attenuator. The positive digital supply rail. Digital levels and voltages are dependent upon this supply. This pin should be decoupled to VSS by a capacitor.
13
VBIAS
O/P
14
N/C
15 16 17 18
DACOUT1 DACOUT2 DACOUT3
O/P O/P O/P N/C
19
AVDD
POWER
20 21 22 23 24
MOD1 IN MOD2 IN MOD1 MOD2 DVDD
I/P I/P O/P O/P POWER
Notes: I/P = O/P =
Input Output
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1.4
External Components
C1 C2 C3 C4 C5
22pF 22pF 0.1F 0.1F 0.1F
20% 20% 20% 20% 20%
R1 R2
1M: 22k:
5% 10%
X1
Note 1
Notes:
1. If an external clock is to be used, it should be connected to Pin 2 and the components C1, C2, R1 and X1 omitted. The ADC clock frequency is derived from the crystal or external clock by means of internal programmable dividers. Refer to Section 1.7 for details of crystal or external clock frequency range.
Figure 2: Recommended External Components
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1.5
General Description
The device comprises four groups of related functions: variable attenuators, digital to analogue converters, a multiplexed analogue to digital converter with multiplexer, clock generator and four 8-bit magnitude comparators with variable reference levels. These functions are all controlled by the 'C-BUS' serial interface and are described below: Variable Attenuators The two variable attenuators have a range of 0 to -12dB and 0 to -6dB respectively and may be controlled independently. Digital to Analogue Converters Three DACs are provided with default resolutions of 8 bits, which are defined at the initial chip reset. In this mode the 'C-BUS' data is transferred in a single byte. An option is provided to define any one or more of the DAC resolutions to be 10 bits, then the DAC requires the transfer of two 'C-BUS' data bytes. The upper and lower DAC reference voltages are defined internally as AVDD and VSS respectively. The output voltage is expressed as: VOUT = AVDD x (DATA / 2n) [Volts] Where, n is the DAC resolution (8 or 10 bits) and DATA is the decimal value of the input code. For example: n = 8 and binary code = 11111111 therefore DATA = 255 VOUT = AVDD x (255 / 256) [Volts] Any one of the three DAC input latches may be loaded by sending an address/command byte followed by one or two data bytes to the 'C-BUS' interface. The data is then latched and the static voltage is updated at the appropriate output. When a DAC is disabled its output is defined as open-circuit. Analogue to Digital Converter and ADC Clock Generator A single successive approximation ADC is provided with four multiplexed inputs. In order to minimise the sampling time of each input channel, a Sample and Hold circuit has not been included at the input of the ADC. For the sampling to be accurate the input signal should not change significantly during the conversion time. Since the typical application is for the monitoring of slowly changing control voltages this should not present any problems. The maximum signal 'linear rate of change', 'S', can be quantified by the following expression (for a maximum 1 bit error): S = AVDD x fadc_clk / (210 x 1000 x (10 + 2)) [mV/s] Where fadc_clk is the internal ADC clock frequency. The programmable clock generator is intended to be flexible, making use of an external system clock signal or a dedicated crystal. This clock signal is scaled to provide the internal ADC clock frequency (fadc_clk). The user has full control of the frequency scaling factor and this should be chosen such that the input clock frequency, at the XTAL/CLOCK pin, divided by this factor is no more than 1MHz.
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The microcontroller is required to wait during the conversion time, Tconv_max (Figure 3), before issuing a 'READ ADC DATAx' command. If this is not done, then the converted data returned on 'C-BUS' will be the result of the previous conversion on the selected channel. It is possible for the data conversion rate to exceed the reply rate on 'C-BUS'. In such a case, the data returned will be the result of the most recent conversion completed.
Figure 3: Example of a "conversion and read"
* Tconv_max is directly related to the ADC clock frequency, which in turn is set by the external clock frequency and the clock divider. Tconv_max = ((10 + 2) x 'NUMBER OF ENABLED MUX INPUTS' / fadc_clk) [Seconds] Note that after reading the ADC1 data, it is necessary to re-enable the conversion of data by setting Bit 5 of the ADC Control Register to `1'. Magnitude Comparators and Interrupt Request High and low digital comparator reference levels are provided for the four digital magnitude comparators via the 'C-BUS' interface. The digital input to the comparators is provided by the most significant 8 bits of each ADC data. When the sampled data falls outside the high or low digital comparator reference levels the status register is updated and the IRQN pin is pulled low. When a reference level is set to '0', its IRQ is disabled.
1.5.1
Software Description Address/Commands Instructions and Data are transferred via the 'C-BUS' in accordance with the timing information given in Figure 4. Instruction and data transactions to and from the FX839 consist of an Address/Command byte followed by either: (i) (ii) a control or DAC data write (1 or 2 bytes) or, a status or ADC data read (1 or 2 bytes)
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Write Only Register (8-Bit and 16-Bit)
HEX ADDRESS/ COMMAND $01 $D0 $D2
REGISTER NAME RESET CLOCK/IRQ CONTROL VARIABLE ATTENUATOR (1) VARIABLE ATTENUATOR (2) DAC CONTROL DAC1 DATA (1) *See Note 1 (2) DAC2 DATA (1) *See Note 1 (2) DAC3 DATA (1) *See Note 1 (2) ADC CONTROL MAG COMP ONE LEVELS (1) MAG COMP ONE LEVELS (2) MAG COMP TWO LEVELS (1) MAG COMP TWO LEVELS (2) MAG COMP THREE LEVELS (1) MAG COMP THREE LEVELS (2) MAG COMP FOUR LEVELS (1) MAG COMP FOUR LEVELS (2)
BIT 7 (D7) N/A 0 0 0 NBIT DAC1 BIT 7 0 BIT 7 0 BIT 7 0 0 BIT 7 BIT 7 BIT 7 BIT 7 BIT 7 BIT 7 BIT 7 BIT 7
BIT 6 (D6) N/A 0 0 0 NBIT DAC2 BIT 6 0 BIT 6 0 BIT 6 0 1 BIT 6 BIT 6 BIT 6 BIT 6 BIT 6 BIT 6 BIT 6 BIT 6
BIT 5 (D5) N/A 0 MOD1 ENABLE MOD2 ENABLE NBIT DAC3 BIT 5 0 BIT 5 0 BIT 5 0
BIT 4 (D4) N/A 0 BIT 4 BIT 4 0 BIT 4 0 BIT 4 0 BIT 4
BIT 3 (D3) N/A 0 BIT 3 BIT 3 DAC1 ENABLE BIT 3 0 BIT 3 0 BIT 3
BIT 2 (D2) N/A BIT 2 MOD1 BIT 2 MOD2 BIT 2 DAC2 ENABLE BIT 2 0 BIT 2 0 BIT 2
BIT 1 (D1) N/A DIVIDER BIT 1 BIT 1 BIT 1 DAC3 ENABLE BIT 1 BIT 9 BIT 1 BIT 9 BIT 1 BIT 9 ADCIN4 ACTIVE BIT 1 BIT 1 BIT 1 BIT 1 BIT 1 BIT 1 BIT 1 BIT 1
BIT 0 (D0) N/A BIT 0 BIT 0 BIT 0 0 BIT 0 BIT 8 BIT 0 BIT 8 BIT 0 BIT 8 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0 BIT 0
$D3 $D4
$D5
$D6
$D7 $D8
$D9
$DA
$DB
0 0 0 ADCIN1 ADCIN2 ADCIN3 READN ACTIVE ACTIVE ACTIVE MAGNITUDE COMPARATOR UPPER LEVEL BIT 5 BIT 4 BIT 3 BIT 2 MAGNITUDE COMPARATOR LOWER LEVEL BIT 5 BIT 4 BIT 3 BIT 2 MAGNITUDE COMPARATOR UPPER LEVEL BIT 5 BIT 4 BIT 3 BIT 2 MAGNITUDE COMPARATOR LOWER LEVEL BIT 5 BIT 4 BIT 3 BIT 2 MAGNITUDE COMPARATOR UPPER LEVEL BIT 5 BIT 4 BIT 3 BIT 2 MAGNITUDE COMPARATOR LOWER LEVEL BIT 5 BIT 4 BIT 3 BIT 2 MAGNITUDE COMPARATOR UPPER LEVEL BIT 5 BIT 4 BIT 3 BIT 2 MAGNITUDE COMPARATOR LOWER LEVEL BIT 5 BIT 4 BIT 3 BIT 2
Note 1:
A second byte is expected by the 'C-BUS' interface only when the 'NBIT DACn' bit of the 'DAC Control Register' is set high. Otherwise the data transfer is a single byte (Bit 7 to Bit 0).
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Read Only Registers (8-Bit and 16-Bit)
HEX ADDRESS/ COMMAND $D1 $DC
REGISTER NAME IRQ FLAGS ADC DATA1 (1) (2) ADC DATA2 (1) (2) ADC DATA3 (1) (2) ADC DATA4 (1) (2)
BIT 7 (D7) HIRQF4 BIT 7 0 BIT 7 0 BIT 7 0 BIT 7 0
BIT 6 (D6) LIRQF4 BIT 6 0 BIT 6 0 BIT 6 0 BIT 6 0
BIT 5 (D5) HIRQF3 BIT 5 0 BIT 5 0 BIT 5 0 BIT 5 0
BIT 4 (D4) LIRQF3 BIT 4 0 BIT 4 0 BIT 4 0 BIT 4 0
BIT 3 (D3) HIRQF2 BIT 3 0 BIT 3 0 BIT 3 0 BIT 3 0
BIT 2 (D2) LIRQF2 BIT 2 0 BIT 2 0 BIT 2 0 BIT 2 0
BIT 1 (D1) HIRQF1 BIT 1 BIT 9 BIT 1 BIT 9 BIT 1 BIT 9 BIT 1 BIT 9
BIT 0 (D0) LIRQF1 BIT 0 BIT 8 BIT 0 BIT 8 BIT 0 BIT 8 BIT 0 BIT 8
$DD
$DE
$DF
Write Only Register Description RESET Register (Hex Address $01) The reset command has no data attached to it. It sets the device registers into the specific states listed below:
REGISTER NAME CLOCK/IRQ CONTROL DAC CONTROL DAC1 DATA1 DAC2 DATA1 DAC3 DATA1 ADC CONTROL VARIABLE ATTENUATOR MAG COMP ONE LEVELS MAG COMP TWO LEVELS MAG COMP THREE LEVELS MAG COMP FOUR LEVELS
(1) (2) (1) (2) (1) (2) (1) (2) (1) (2)
BIT 7 (D7) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT 6 (D6) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT 5 (D5) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT 4 (D4) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT 3 (D3) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT 2 (D2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT 1 (D1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT 0 (D0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note 1:
Default resolution is defined as 8-Bits.
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CLOCK/IRQ CONTROL Register (Hex Address $D0) This register controls the ADC clock divide ratio: Bits 7 to 3 DIVIDER (Bit 2 to Bit 0) Reserved for future use. These bits should be set to '0'. The input clock divide ratio, which sets the ADC clock frequency is defined in the following table: Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 Function Powersave /1 /2 /4 /8 /16 /32 /64
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VARIABLE ATTENUATOR Register (Hex address $D2) This is a 16-bit register. Byte (1) is sent first. Bits 0 - 5 of the first byte in this register are used to enable and set the attenuation of the Modulator 1 amplifier and bits 0 - 5 of the second byte in this register are used to enable and set the attenuation of the Modulator 2 amplifier, according to the tables below:
BYTE 1
5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mod. 1 Attenuation Disabled (VBIAS) >40dB 12.0dB 11.6dB 11.2dB 10.8dB 10.4dB 10.0dB 9.6dB 9.2dB 8.8dB 8.4dB 8.0dB 7.6dB 7.2dB 6.8dB 6.4dB 6.0dB 5.6dB 5.2dB 4.8dB 4.4dB 4.0dB 3.6dB 3.2dB 2.8dB 2.4dB 2.0dB 1.6dB 1.2dB 0.8dB 0.4dB 0dB 5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
BYTE 2
1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mod. 2 Attenuation Disabled (VBIAS) >40dB 6.0dB 5.8dB 5.6dB 5.4dB 5.2dB 5.0dB 4.8dB 4.6dB 4.4dB 4.2dB 4.0dB 3.8dB 3.6dB 3.4dB 3.2dB 3.0dB 2.8dB 2.6dB 2.4dB 2.2dB 2.0dB 1.8dB 1.6dB 1.4dB 1.2dB 1.0dB 0.8dB 0.6dB 0.4dB 0.2dB 0dB
X = don't care
MOD1 ENABLE (Bit 5, first byte) MOD2 ENABLE (Bit 5, second byte) (Bits 7 and 6, first and second bytes)
When this bit is '1' the MOD1 attenuator is enabled. When this bit is '0' the MOD1 attenuator is disabled (i.e. powersaved). When this bit is '1' the MOD2 attenuator is enabled. When this bit is '0' the MOD2 attenuator is disabled (i.e. powersaved). Reserved for future use. These should be set to '0'.
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DAC CONTROL Register (Hex address $D3) This register controls the resolution and the number of enabled DAC outputs: NBIT DAC1, NBIT DAC2, NBIT DAC3 These bits define the input resolutions for each of the four DACs. When 'NBIT (Bit 7 to Bit 5) DACn' is '0' the resolution of DACn is 8-Bits. When 'NBIT DACn is '1' the resolution of DACn is 10-Bits. Bit 4 Reserved for future use. This bit should be set to '0'.
DAC1 ENABLE, DAC2 ENABLE, DAC3 ENABLE These bits allow any one or more of the three DACs to be powered up. When '0' (Bit 3 to Bit 1) the DACn is powered down and the output is high impedance. When '1' the DAC is powered on and the output voltage is defined by the DAC Data Registers. Bit 0 Reserved for future use. This bit should be set to '0'.
DAC1 DATA Register (Hex Address $D4) DAC2 DATA Register (Hex Address $D5) DAC3 DATA Register (Hex Address $D6) The data in these three registers sets the analogue voltage at the output of DAC1, DAC2 and DAC3. This data will consist of one or two bytes depending on the defined input resolution which is set by bits 7, 6 and 5 of the DAC Control Register. When operating with 10-bit resolution Bit 7 to Bit 2 of the DACn DATA Register second data byte must be set to "0".
ADC CONTROL Register (Hex Address $D7) This register controls the resolution, active inputs and conversion modes of the ADC as described below: Bit 7 Bit 6 Reserved for future use. This bit should be set to '0'. Reserved for future use. This bit should be set to `1'. (On reset, this bit is set to `0'). When this bit is set to '1' all active input channels are continuously sampled and the latest converted data stored for each channel. When this bit is set to `0' all conversions are stopped so that they may be read.
READN (Bit 5)
ADC1 ACTIVE, ADC2 ACTIVE, ADC3 ACTIVE, ADC4 ACTIVE These bits allow any one or more of the four ADC input channels to be enabled. (Bit 4 to Bit 1) When '0' the ADCINn input voltage is not converted. When '1' the ADCINn input is defined as active and the input voltage is converted. Note: ADC1 must always be enabled for any other channel to work. (Bit 0) Reserved for future use. This bit should be set to `0'.
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MAG COMP ONE LEVELS MAG COMP TWO LEVELS MAG COMP THREE LEVELS MAG COMP FOUR LEVELS
(Hex Address $D8) (Hex Address $D9) (Hex Address $DA) (Hex Address $DB)
Each address controls the relevant numbered ADC magnitude comparator. The first byte, transmitted with the most significant bit first, sets the magnitude comparator upper reference level and the second byte sets the magnitude comparator lower reference level. When a reference level's value is set to '0' its IRQ is disabled. If a reference level's value is set to `FF', the level will correspond to: VREF = AVDD x (255 / 256) [Volts]
Read Only Register Description IRQ FLAGS Register (Hex Address $D1) HIRQF1, HIRQF2, HIRQF3, HIRQF4 (Bit 1) (Bit 3) (Bit 5) (Bit 7) These bits are set if the relevant digital magnitude comparator input exceeds its upper reference level. These bits are reset to '0' immediately after reading the IRQ FLAGS register. When any of these bits are set, an interrupt will be generated if the relevant reference level is not zero. LIRQF1, LIRQF2, LIRQF3, LIRQF4 (Bit 0) (Bit 2) (Bit 4) (Bit 6) These bits are set if the relevant digital magnitude comparator input falls below its lower reference level. These bits are reset to '0' immediately after reading the IRQ FLAGS register. When any of these bits are set, an interrupt will be generated if the relevant reference level is not zero.
ADC DATA1 Register (Hex Address $DC) ADC DATA2 Register (Hex Address $DD) ADC DATA3 Register (Hex Address $DE) ADC DATA4 Register (Hex Address $DF) This data will consist of two bytes each. Bit 7 to Bit 2 of the second data byte will be set to '0'.
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1.6
1.6.1
Application Notes
General
1.6.1.1 `C-BUS' Clock Although this is specified as a 500kHz clock for compatibility with other `C-BUS' devices, the FX839 `CBUS' will operate over a much wider range. Users should ensure that the `C-BUS' clock is at least 4 times slower than the crystal or external clock on Pin 2 of the FX839.
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1.7
1.7.1
Performance Specification
Electrical Performance
Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. -0.3 -0.3 -30 -20 -100 Max. 7.0 VDD + 0.3 +30 +20 +100 Units V V mA mA mV
Supply (VDD - VSS) (either AVDD or DVDD) Voltage on any pin to VSS Current into or out of AVDD, DVDD and VSS pins Current into or out of any other pin AVDD - DVDD
P4/D2 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature
Min.
-55 -40
Max. 800 13 +125 +85
Units mW mW/C C C
D5 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature
Min.
-55 -40
Max. 550 9 +125 +85
Units mW mW/C C C
Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) (either AVDD or DVDD) Operating Temperature Xtal Frequency Min. 3.0 -40 0.5 Max. 5.5 +85 6.0 Units V C MHz
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Operating Characteristics For the following conditions unless otherwise specified: AVDD = DVDD = VDD = 3.3V to 5.0V, Tamb = - 40C to +85C. Notes DC Parameters Supply Voltage (DVDD) Supply Voltage (AVDD) Supply Difference (AVDD - DVDD) VDD = 5V IDD (powersaved) VDD = 5V IDD (not powersaved) VDD = 3.3V IDD (powersaved) VDD = 3.3V IDD (not powersaved) 'C-BUS' Interface Input Logic '1' Input Logic '0' Input Leakage Current (Logic '1' and '0') Input Capacitance Output Logic '1' (IOH = 120A) Output Logic '0' (IOL = 360A) DACs and Output Buffers (Guaranteed monotonic) (a) Un-loaded Performance Resolution Internal DAC Settling Time (to 0.5 lsb) Integral non-linearity (8-Bit mode) Integral non-linearity (10-Bit mode) Differential non-linearity (8-Bit mode) Differential non-linearity (10-Bit mode) Buffer Slew Rate (with 20pF load) Buffer Output Resistance (open loop) Zero Error RMS Output Noise Voltage (Low Pass Filter of 30kHz bandwidth) (b) Loaded Performance Output voltage with resistive load to ground (Digital code = 3FFHEX) Output voltage with resistive load to ground (Digital code = 200HEX, 10 Bit) or (Digital code = 80HEX, 8 Bit) Output voltage with resistive load to VDD (Digital code = 000HEX) Minimum Resistive Load 1 4.79 V 8 or 10 6 6 5 5 10.0 3.0 5.0 1.0 1.0 TBD 200 20 Bits s LSBs LSBs LSBs LSBs V/s mV V Min. Typ. Max. Units
3.0 3.0 -100 -
5.0 5.0 250 4.5 150 2.5
5.5 5.5 100 400 7.0 250 4.0
V V mV A mA A mA
70% -1.0 90% 10% 30% 1.0 7.5
DVDD DVDD A pF DVDD DVDD
-20
0 10
3
2.495
V
3 1.0
200
mV k
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Notes ADCs and Multiplexed Inputs (Guaranteed monotonic) Resolution Input signal 'linear rate of change' VDD = 3.3V, fadc_clk = (For 1 Bit error) Conversion Time fadc_clk = 1MHz Integral non-linearity Differential non-linearity Zero error ADC Clock Frequency (fadc_clk) Input Capacitance Variable Attenuators Nominal Adjustment Range Attenuation Accuracy Step Size Output Impedance Bandwidth (-3dB) Input Impedance (at 100Hz) Magnitude Comparators and Interrupt Request Resolution Output Logic '0' at IRQN (IOL= 360A and R2 = 22k 10% to DVDD) 'Off' State Leakage Current at IRQN (Vout = DVDD) Xtal/Clock Input Frequency Range 'High' pulse width 'Low' pulse width Input Impedance (at 100Hz) Gain (I/P = 1mVrms at 100Hz) 4 (MOD1) (MOD2) (MOD1) (MOD2) 2 2
Min.
Typ.
Max.
Units
10 0.27
Bits mV/s
12 2.0 1.0 20 TBD
-20 1.0 TBD
s LSBs LSBs mV MHz pF
0 0 -1.0 0.2 0.1
0.4 0.2 600 100 15.0
12.0 6.0 1.0 0.6 0.3
dB dB dB dB dB kHz k
8 10% 10
Bits DVDD A
0.5 40 40 10 20
6.0
MHz ns ns M dB
Notes:
1. The extremes of the DAC output range, when resistively loaded, are affected by the output impedance of the DAC buffer. Under these conditions the output impedance can approach 200. However, when the output is operating well within the supply, the closed loop output impedance will be significantly lower thereby improving the loaded performance. 2. Small signal impedance, at AVDD = 5V and Tamb = 25C.
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FX839
Notes:
3. RLOAD = 5k AVDD = 5.0V. 4. At VDD = 5.0V only. The `C-BUS' clock must be at least 4 times slower than this xtal/clock frequency. 5. Differential non-linearity is defined as the difference in width between adjacent code midpoints and the width of an ideal LSB, divided by the width of an ideal LSB. 6. Integral non-linearity is defined as the width difference between an actual code midpoint and the line of best fit through all code midpoints, divided by the width of an ideal LSB.
(c) 1997 Consumer Microcircuits Limited
19
D/839/4
Analogue Control Interface
FX839
1.7.1
Electrical Performance (continued) Timing Diagrams
Figure 4: 'C-BUS' Timing
For the following conditions unless otherwise specified: DVDD = 3.3V to 5.0V, Tamb = -40C to +85C. Parameter tCSE tCSH tHIZ tCSOFF tNXT tCK "CS-Enable to Clock-High" Last "Clock-High to CS-High" "CS-High to Reply Output 3-state" "CS-High" Time between transactions "Inter-Byte" Time "Clock-Cycle" time Notes Min. 2.0 4.0 2.0 4.0 2.0 Typ. Max. 2.0 Units s s s s s s
Notes:
1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB (Bit 0) last. 2. Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge. 3. Loaded commands are acted upon at the end of each command. 4. To allow for differing Controller serial interface formats 'C-BUS' compatible ICs are able to work with either polarity SERIAL CLOCK pulses.
(c) 1997 Consumer Microcircuits Limited
20
D/839/4
Analogue Control Interface
FX839
1.7.2
Packaging
Figure 5: D2 Mechanical Outline: Order as part no. FX839D2
Figure 6: D5 Mechanical Outline: Order as part no. FX839D5
(c) 1997 Consumer Microcircuits Limited
21
D/839/4
Analogue Control Interface
FX839
1.7.2
Packaging
Figure 7: P4 Mechanical Outline: Order as part no. FX839P4
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.
CONSUMER MICROCIRCUITS LIMITED
1 WHEATON ROAD WITHAM - ESSEX CM8 3TD - ENGLAND Telephone: Telefax: e-mail: +44 1376 513833 +44 1376 518247 sales@cmlmicro.co.uk http://www.cmlmicro.co.uk

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